The need to provide facilities for processing sequences of vector elements was recognised in the very early days of digital computer design. The von Neumann concept, for example, included the notion of allowing instructions to be treated as data, which meant that the address part of an instruction accessing a vector element could be incremented during the execution of a program loop and thus produce the effect of processing a vector. In practice, however, this technique allows so much scope for program error that even the very first stored program computer (the Manchester Mark 1) used B-lines instead, and this latter technique has been used almost universally ever since. Thus virtually any digital computer can be used to process vectors. The differences between machines lie in the addressing facilities which they provide to support accesses to data structures, and whether or not they include instructions which implicitly process a sequence of vector elements. Computers with this latter facility have been described by Flynn [Fly72] as Single Instruction Multiple Data (SIMD) arrangements, in contrast with the Single Instruction Single Data (SISD) arrangement of conventional computers. In fact SIMD systems may be further subdivided into Vector Processors and Array Processors. Systems in this latter category are dealt with in Volume II of this book. We have already met one example of an SIMD vector machine in the TI ASC (section 4.3); in this chapter we shall examine the CRAY series of computers.
|Title of host publication||Architecture of High Performance Computers|
|Subtitle of host publication||Volume I Uniprocessors and vector processors|
|Place of Publication||New York, NY|
|Publisher||Springer New York|
|Number of pages||27|
|Publication status||Published - 1989|