The design and performance of a conflict-avoiding cache

N. Topham; A. Gonzalez; J. Gonzalez

doi:10.1109/MICRO.1997.645799

The design and performance of a conflict-avoiding cache

N. Topham, A. Gonzalez, J. Gonzalez

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

High performance architectures depend heavily on efficient multi-level memory hierarchies to minimize the cost of accessing data. This dependence will increase with the expected increases in relative distance to main memory. There have been a number of published proposals for cache conflict-avoidance schemes. We investigate the design and performance of conflict-avoiding cache architectures based on polynomial modulus functions, which earlier research has shown to be highly effective at reducing conflict miss ratios. We examine a number of practical implementation issues and present experimental evidence to support the claim that pseudo-randomly indexed caches are both effective in performance terms and practical from an implementation viewpoint

Original language	English
Title of host publication	Microarchitecture, 1997. Proceedings., Thirtieth Annual IEEE/ACM International Symposium on
Pages	71-80
Number of pages	10
DOIs	https://doi.org/10.1109/MICRO.1997.645799
Publication status	Published - 1 Dec 1997

Keywords

cache storage
memory architecture
performance evaluation
polynomials
cache architecture design
conflict miss ratios
conflict-avoiding cache performance
data access cost minimization
high performance architectures
main memory
multi-level memory hierarchies
polynomial modulus functions
Costs
Indexing
Pathology
Polynomials
Robustness

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10.1109/MICRO.1997.645799

Topham et al 1997 The Design and PerformanceAccepted author manuscript, 94 KB

http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=645799

Cite this

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title = "The design and performance of a conflict-avoiding cache",

abstract = "High performance architectures depend heavily on efficient multi-level memory hierarchies to minimize the cost of accessing data. This dependence will increase with the expected increases in relative distance to main memory. There have been a number of published proposals for cache conflict-avoidance schemes. We investigate the design and performance of conflict-avoiding cache architectures based on polynomial modulus functions, which earlier research has shown to be highly effective at reducing conflict miss ratios. We examine a number of practical implementation issues and present experimental evidence to support the claim that pseudo-randomly indexed caches are both effective in performance terms and practical from an implementation viewpoint",

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N2 - High performance architectures depend heavily on efficient multi-level memory hierarchies to minimize the cost of accessing data. This dependence will increase with the expected increases in relative distance to main memory. There have been a number of published proposals for cache conflict-avoidance schemes. We investigate the design and performance of conflict-avoiding cache architectures based on polynomial modulus functions, which earlier research has shown to be highly effective at reducing conflict miss ratios. We examine a number of practical implementation issues and present experimental evidence to support the claim that pseudo-randomly indexed caches are both effective in performance terms and practical from an implementation viewpoint

AB - High performance architectures depend heavily on efficient multi-level memory hierarchies to minimize the cost of accessing data. This dependence will increase with the expected increases in relative distance to main memory. There have been a number of published proposals for cache conflict-avoidance schemes. We investigate the design and performance of conflict-avoiding cache architectures based on polynomial modulus functions, which earlier research has shown to be highly effective at reducing conflict miss ratios. We examine a number of practical implementation issues and present experimental evidence to support the claim that pseudo-randomly indexed caches are both effective in performance terms and practical from an implementation viewpoint

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KW - memory architecture

KW - performance evaluation

KW - polynomials

KW - cache architecture design

KW - conflict miss ratios

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KW - data access cost minimization

KW - high performance architectures

KW - main memory

KW - multi-level memory hierarchies

KW - polynomial modulus functions

KW - Costs

KW - Indexing

KW - Pathology

KW - Polynomials

KW - Robustness

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DO - 10.1109/MICRO.1997.645799

M3 - Conference contribution

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BT - Microarchitecture, 1997. Proceedings., Thirtieth Annual IEEE/ACM International Symposium on

ER -

The design and performance of a conflict-avoiding cache

Abstract

Keywords

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