Abstract
High performance architectures depend heavily on efficient multi-level memory hierarchies to minimize the cost of accessing data. This dependence will increase with the expected increases in relative distance to main memory. There have been a number of published proposals for cache conflict-avoidance schemes. We investigate the design and performance of conflict-avoiding cache architectures based on polynomial modulus functions, which earlier research has shown to be highly effective at reducing conflict miss ratios. We examine a number of practical implementation issues and present experimental evidence to support the claim that pseudo-randomly indexed caches are both effective in performance terms and practical from an implementation viewpoint
Original language | English |
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Title of host publication | Microarchitecture, 1997. Proceedings., Thirtieth Annual IEEE/ACM International Symposium on |
Pages | 71-80 |
Number of pages | 10 |
DOIs | |
Publication status | Published - 1 Dec 1997 |
Keywords
- cache storage
- memory architecture
- performance evaluation
- polynomials
- cache architecture design
- conflict miss ratios
- conflict-avoiding cache performance
- data access cost minimization
- high performance architectures
- main memory
- multi-level memory hierarchies
- polynomial modulus functions
- Costs
- Indexing
- Pathology
- Polynomials
- Robustness