The Mondrian Data Engine

Mario Drumond, Alexandros Daglis, Nooshin S. Mirzadeh, Dmitrii Ustiugov, Javier Picorel, Babak Falsafi, Boris Grot, Dionisios N. Pnevmatikatos

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

The increasing demand for extracting value out of ever-growing data poses an ongoing challenge to system designers, a task only made trickier by the end of Dennard scaling. As the performance density of traditional CPU-centric architectures stagnates, advancing compute capabilities necessitates novel architectural approaches. Near-memory processing (NMP) architectures are reemerging as promising candidates to improve computing efficiency through tight coupling of logic and memory. NMP architectures are especially fitting for data analytics, as they provide immense bandwidth to memory-resident data and dramatically reduce data movement, the main source of energy consumption.

Modern data analytics operators are optimized for CPU execution and hence rely on large caches and employ random memory accesses. In the context of NMP, such random accesses result in wasteful DRAM row buffer activations that account for a significant fraction of the total memory access energy. In addition, utilizing NMP's ample bandwidth with fine-grained random accesses requires complex hardware that cannot be accommodated under NMP's tight area and power constraints. Our thesis is that efficient NMP calls for an algorithm-hardware co-design that favors algorithms with sequential accesses to enable simple hardware that accesses memory in streams. We introduce an instance of such a co-designed NMP architecture for data analytics, the Mondrian Data Engine. Compared to a CPU-centric and a baseline NMP system, the Mondrian Data Engine improves the performance of basic data analytics operators by up to 49x and 5x, and efficiency by up to 28x and 5x, respectively.
Original languageEnglish
Title of host publicationISCA '17 Proceedings of the 44th Annual International Symposium on Computer Architecture
PublisherACM
Pages639-651
Number of pages13
ISBN (Print)978-1-4503-4892-8
DOIs
Publication statusPublished - 28 Jun 2017
Event44th International Symposium on Computer Architecture (ISCA) - Sheraton Hotel, Toronto, Canada
Duration: 24 Jun 201728 Jun 2017
Conference number: 39559

Publication series

NameACM SIGARCH Computer Architecture News
PublisherACM
Number2
Volume45
ISSN (Electronic)0163-5964

Conference

Conference44th International Symposium on Computer Architecture (ISCA)
Abbreviated titleISCA
Country/TerritoryCanada
CityToronto
Period24/06/1728/06/17

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