The Reconfigurable Instruction Cell Array

S. Khawam, I. Nousias, M. Milward, Y. Yi, M. Muir, Tughrul Arslan

Research output: Contribution to journalArticlepeer-review

Abstract

This paper presents a novel instruction cell-based reconfigurable computing architecture for low-power applications, thereafter referred to as the reconfigurable instruction cell array (RICA). For the development of the RICA, a top-down software driven approach was taken and revealed as one of the key design decisions for a flexible, easy to program, low-power architecture. These features make RICA an architecture that inherently solves the main design requirements of modern low-power devices. Results show that it delivers considerably less power consumption when compared to leading VLIW and low-power digital signal processors, but still maintaining their throughput performance.
Original languageEnglish
Pages (from-to)75-85
Number of pages11
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume16
Issue number1
DOIs
Publication statusPublished - 1 Jan 2008

Keywords

  • Dynamic reconfiguration
  • parallel processing
  • reconfigurable computing

Fingerprint Dive into the research topics of 'The Reconfigurable Instruction Cell Array'. Together they form a unique fingerprint.

Cite this