The scalability of decoupled multiprocessors

T.J. Harris, N.P. Topham

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

We consider the ability of the technique of decoupling to improve the scalability of multiprocessors which have physically distributed memory but which support a shared memory model of computation. We consider the performance of a variety of similar such architectures; those with and without caching and those with and without decoupling. As a metric of scalability we focus on the speedup of these architectures while executing a suite of parallel scientific applications. We show that decoupling can play a substantial role in improving the scalability of such an architecture. Furthermore the additional technique of caching with hardware coherence can further improve this scalability in the face of high latency memory access.
Original languageEnglish
Title of host publicationScalable High-Performance Computing Conference, 1994., Proceedings of the
Pages17-22
Number of pages6
DOIs
Publication statusPublished - 1 May 1994

Keywords

  • distributed memory systems
  • performance evaluation
  • protocols
  • shared memory systems
  • storage management
  • caching
  • decoupled multiprocessors
  • distributed memory
  • latency memory access
  • parallel scientific applications
  • performance
  • scalability
  • scalability metric
  • shared memory model
  • Computer architecture
  • Computer science
  • Concurrent computing
  • Delay effects
  • Distributed computing
  • Hardware
  • Parallel processing
  • Parallel programming
  • Physics computing
  • Scalability

Fingerprint Dive into the research topics of 'The scalability of decoupled multiprocessors'. Together they form a unique fingerprint.

Cite this