The Smart Cache: An Energy-Efficient Cache Architecture Through Dynamic Adaptation

Karthik T. Sundararajan, Timothy M. Jones, Nigel P. Topham

Research output: Contribution to journalArticlepeer-review


The demand for low-power embedded systems requires designers to tune processor parameters to avoid excessive energy wastage. Tuning on a per-application or per-application-phase basis allows a greater saving in energy consumption without a noticeable degradation in performance. On-chip caches often consume a significant fraction of the total energy budget and are therefore prime candidates for adaptation. Fixed-configuration caches must be designed to deliver low average memory access times across a wide range of potential applications. However, this can lead to excessive energy consumption for applications that do not require the full capacity or associativity of the cache at all times. Furthermore, in systems where the clock period is constrained by the access times of level-1 caches, the clock frequency for all applications is effectively limited by the cache requirements of the most demanding phase within the most demanding application. This results in both performance and energy efficiency that represents the lowest common denominator across the applications. In this work we present a Set and way Management cache Architecture for Run-Time reconfiguration (SMART cache), a cache architecture that allows reconfiguration in both its size and associativity. Results show the energy-delay of the Smart cache is on average 70 and 12% better than the baseline configuration for a two-core and four-core system respectively, with just 2% away from oracle result and also with an overall performance degradation of less than 2% compared with a baseline statically-configured cache.

Original languageEnglish
Pages (from-to)305-330
Number of pages26
JournalInternational journal of parallel programming
Issue number2
Publication statusPublished - Apr 2013


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