Towards a dynamic associativity enabled write prediction based hybrid cache

Sukarn Agarwal, Hemangee K. Kapoor

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Non-Volatile Memory (NVM) technologies such as Spin Transfer Torque Random Access Memory (STT-RAM), Phase Change Random Access Memory (PCRAM) and Resistive Random Access Memory (RERAM) have emerged as a potential replacement for traditional SRAM as the last level cache. These are attractive due to their low static power consumption, higher density and good scalability. However, expensive write operations in these NVMs reduces their chances as a substitute for SRAM. To handle these expensive write operations, cache is designed as a hybrid cache consisting of different memory technologies. This paper proposes a block prediction technique for hybrid cache that is based on existing prediction mechanism. The hybrid cache has a smaller SRAM partition which may limit the amount of cache capacity. This is overcome by increasing or decreasing the associativity dynamically. The proposed policy is compared with the baseline SRAM and STT-RAM caches. Experimental results using full system simulation shows significant reduction of the energy with slight improvement of performance.
Original languageEnglish
Title of host publication2016 20th International Symposium on VLSI Design and Test (VDAT)
PublisherIEEE
Pages1-6
Number of pages6
ISBN (Electronic)978-1-5090-1422-4
ISBN (Print)978-1-5090-1423-1
DOIs
Publication statusPublished - 12 Oct 2017
Event20th International Symposium on VLSI Design and Test - Guwahati, India
Duration: 24 May 201627 May 2016
Conference number: 20

Publication series

NameInternational Symposium on VLSI Design and Test (VDAT)
PublisherIEEE
ISSN (Print)2475-8620
ISSN (Electronic)2768-0800

Conference

Conference20th International Symposium on VLSI Design and Test
Abbreviated titleVDAT 2016
Country/TerritoryIndia
CityGuwahati
Period24/05/1627/05/16

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