Towards a Secure Partial Reconfiguration of Xilinx FPGAs

Adewale Adetomi, Godwin Enemali, Tughrul Arslan

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

The susceptibility of Field Programmable Gate Arrays (FPGAs) to power analysis attacks has gained more attention lately. While this was predicted a long time ago, it was not until recently that successful attacks were reported. Xilinx FPGA families before the UltraScale architecture offer little when it comes to protecting the encryption keys from being retrieved via power analysis attacks. In this paper, we propose a scheme for securing Xilinx FPGAs against these attacks by using the on-chip Xilinx Analog-to-Digital Converter (XADC) to monitor the power consumption of the chip during an encrypted partial bitstream configuration. Our proposed solution to power analysis attacks involves activating or deactivating power consumer circuits to level out the power consumption of the FPGA with the aim of masking the power signature of the encryption key. We present here our implementation strategy and preliminary power consumption measurements of FPGA primitives that can be used to achieve this objective.

Original languageEnglish
Title of host publication2018 NASA/ESA CONFERENCE ON ADAPTIVE HARDWARE AND SYSTEMS (AHS 2018)
PublisherIEEE PES
Pages174-178
Number of pages5
ISBN (Electronic)978-1-5386-7753-7
DOIs
Publication statusPublished - 22 Nov 2018
EventNASA/ESA Conference on Adaptive Hardware and Systems (AHS) - Edinburgh
Duration: 6 Aug 20189 Aug 2018

Publication series

NameNASA/ESA Conference on Adaptive Hardware and Systems
PublisherIEEE
ISSN (Print)1939-7003

Conference

ConferenceNASA/ESA Conference on Adaptive Hardware and Systems (AHS)
CityEdinburgh
Period6/08/189/08/18

Keywords

  • Side-channel attack
  • Power analysis attack
  • SPA
  • DPA
  • CPA
  • FPGA
  • XADC

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