Towards Optimizing Refresh Energy in Embedded-DRAM Caches Using Private Blocks

Sheel Sindhu Manohar; Sukarn Agarwal; Hemangee K. Kapoor

doi:10.1145/3299874.3317995

Towards Optimizing Refresh Energy in Embedded-DRAM Caches Using Private Blocks

Sheel Sindhu Manohar, Sukarn Agarwal, Hemangee K. Kapoor

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract / Description of output

In recent years, the increased working set size of applications craves for more memory demand in terms of large size Last Level Caches (LLC). To fulfill this, embedded DRAM (eDRAM) caches have been considered as one of the best alternatives over conventional SRAM caches. eDRAM has a property of low leakage and provides more capacity in the same area footprint of SRAM. However, its retention period consumes significant refresh energy in the periodic refresh. In this paper, we present an approach to minimize the total energy spent on refreshes by considering the presence of private blocks in the LLC. Our approach restricts refreshing of those blocks that are loaded exclusively from the main memory on an LLC miss. Experimental result using full system simulation show 55% reduction in the total number of refreshes compared to baseline policy; and 62% reduction in total power consumption over SRAM.

Original language	English
Title of host publication	Proceedings of the 2019 on Great Lakes Symposium on VLSI
Place of Publication	New York, NY, USA
Publisher	ACM Association for Computing Machinery
Pages	225–230
Number of pages	6
ISBN (Print)	9781450362528
DOIs	https://doi.org/10.1145/3299874.3317995
Publication status	Published - 13 May 2019
Event	29th ACM Great Lakes Symposium on VLSI - Washington D.C., United States Duration: 9 May 2019 → 11 May 2019 Conference number: 29 https://www.glsvlsi.org/archive/glsvlsi19/index.html

Publication series

Name	GLSVLSI '19
Publisher	Association for Computing Machinery
ISSN (Print)	1066-1395

Conference

Conference	29th ACM Great Lakes Symposium on VLSI
Abbreviated title	GLSVLSI 2019
Country/Territory	United States
City	Washington D.C.
Period	9/05/19 → 11/05/19
Internet address	https://www.glsvlsi.org/archive/glsvlsi19/index.html

Keywords / Materials (for Non-textual outputs)

embedded dram
private blocks
last level cache
refresh energy

Access to Document

10.1145/3299874.3317995Licence: All Rights Reserved

https://dl.acm.org/doi/10.1145/3299874.3317995Licence: All Rights Reserved

Cite this

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title = "Towards Optimizing Refresh Energy in Embedded-DRAM Caches Using Private Blocks",

abstract = "In recent years, the increased working set size of applications craves for more memory demand in terms of large size Last Level Caches (LLC). To fulfill this, embedded DRAM (eDRAM) caches have been considered as one of the best alternatives over conventional SRAM caches. eDRAM has a property of low leakage and provides more capacity in the same area footprint of SRAM. However, its retention period consumes significant refresh energy in the periodic refresh. In this paper, we present an approach to minimize the total energy spent on refreshes by considering the presence of private blocks in the LLC. Our approach restricts refreshing of those blocks that are loaded exclusively from the main memory on an LLC miss. Experimental result using full system simulation show 55% reduction in the total number of refreshes compared to baseline policy; and 62% reduction in total power consumption over SRAM.",

keywords = "embedded dram, private blocks, last level cache, refresh energy",

author = "Manohar, {Sheel Sindhu} and Sukarn Agarwal and Kapoor, {Hemangee K.}",

year = "2019",

month = may,

day = "13",

doi = "10.1145/3299874.3317995",

language = "English",

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series = "GLSVLSI '19",

publisher = "ACM Association for Computing Machinery",

pages = "225–230",

booktitle = "Proceedings of the 2019 on Great Lakes Symposium on VLSI",

note = "29th ACM Great Lakes Symposium on VLSI, GLSVLSI 2019 ; Conference date: 09-05-2019 Through 11-05-2019",

url = "https://www.glsvlsi.org/archive/glsvlsi19/index.html",

}

Manohar, SS, Agarwal, S & Kapoor, HK 2019, Towards Optimizing Refresh Energy in Embedded-DRAM Caches Using Private Blocks. in Proceedings of the 2019 on Great Lakes Symposium on VLSI. GLSVLSI '19, ACM Association for Computing Machinery, New York, NY, USA, pp. 225–230, 29th ACM Great Lakes Symposium on VLSI, Washington D.C., District of Columbia, United States, 9/05/19. https://doi.org/10.1145/3299874.3317995

Towards Optimizing Refresh Energy in Embedded-DRAM Caches Using Private Blocks. / Manohar, Sheel Sindhu; Agarwal, Sukarn; Kapoor, Hemangee K.
Proceedings of the 2019 on Great Lakes Symposium on VLSI. New York, NY, USA: ACM Association for Computing Machinery, 2019. p. 225–230 (GLSVLSI '19).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - Towards Optimizing Refresh Energy in Embedded-DRAM Caches Using Private Blocks

AU - Manohar, Sheel Sindhu

AU - Agarwal, Sukarn

AU - Kapoor, Hemangee K.

N1 - Conference code: 29

PY - 2019/5/13

Y1 - 2019/5/13

N2 - In recent years, the increased working set size of applications craves for more memory demand in terms of large size Last Level Caches (LLC). To fulfill this, embedded DRAM (eDRAM) caches have been considered as one of the best alternatives over conventional SRAM caches. eDRAM has a property of low leakage and provides more capacity in the same area footprint of SRAM. However, its retention period consumes significant refresh energy in the periodic refresh. In this paper, we present an approach to minimize the total energy spent on refreshes by considering the presence of private blocks in the LLC. Our approach restricts refreshing of those blocks that are loaded exclusively from the main memory on an LLC miss. Experimental result using full system simulation show 55% reduction in the total number of refreshes compared to baseline policy; and 62% reduction in total power consumption over SRAM.

AB - In recent years, the increased working set size of applications craves for more memory demand in terms of large size Last Level Caches (LLC). To fulfill this, embedded DRAM (eDRAM) caches have been considered as one of the best alternatives over conventional SRAM caches. eDRAM has a property of low leakage and provides more capacity in the same area footprint of SRAM. However, its retention period consumes significant refresh energy in the periodic refresh. In this paper, we present an approach to minimize the total energy spent on refreshes by considering the presence of private blocks in the LLC. Our approach restricts refreshing of those blocks that are loaded exclusively from the main memory on an LLC miss. Experimental result using full system simulation show 55% reduction in the total number of refreshes compared to baseline policy; and 62% reduction in total power consumption over SRAM.

KW - embedded dram

KW - private blocks

KW - last level cache

KW - refresh energy

U2 - 10.1145/3299874.3317995

DO - 10.1145/3299874.3317995

M3 - Conference contribution

SN - 9781450362528

T3 - GLSVLSI '19

SP - 225

EP - 230

BT - Proceedings of the 2019 on Great Lakes Symposium on VLSI

PB - ACM Association for Computing Machinery

CY - New York, NY, USA

T2 - 29th ACM Great Lakes Symposium on VLSI

Y2 - 9 May 2019 through 11 May 2019

ER -

Towards Optimizing Refresh Energy in Embedded-DRAM Caches Using Private Blocks

Abstract / Description of output

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Conference

Keywords / Materials (for Non-textual outputs)

Access to Document

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Cite this