Towards the automatic design of more efficient digital circuits

VK Vassilev*, D Job, JF Miller

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract / Description of output

This paper introduces a new methodology of evolving electronic circuits by which the process of evolutionary design is guaranteed to produce a functionally correct solution. The method employs a mapping so represent an electronic circuit on an array of logic cells that is further encoded within a genotype. The mapping is many-to-one and thus there are many genotypes that have equal fitness values. Genotypes with equal fitness values define subgraphs in the resulting fitness landscapes referred to as neutral networks. This is further used in the design of a neutral network that connects the conventional with other more efficient designs. To explore such a network a navigation strategy is defined by which the space of all functionally correct circuits call be explored. The paper shows that very efficient digital circuits can be obtained by evolving from the conventional designs. Results for several binary multiplier circuits such as the three and four-bit multipliers are reported. The evolved solution for the three-bit multiplier consists of 23 two-input logic gates that in terms of number of two-input gates wed is 23.3% more efficient than the most efficient known conventional design. The logic operators required to implement this circuit are 14 ANDs, 9 XORs, and 2 inversions (NOT). The evolved four-bit multiplier consists of 57 two-input logic gates that is 10.9% more efficient (in terms of number of two-input gates used) than the most efficient known conventional design. The optimal size of the target circuits is also studied by measuring the length of the neutral walks from the obtained designs.

Original languageEnglish
Title of host publicationSECOND NASA/DOD WORKSHOP ON EVOLVABLE HARDWARE, PROCEEDINGS
EditorsJ Lohn, A Stoica, D Keymeulen, S Colombano
Place of PublicationLOS ALAMITOS
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
Pages151-160
Number of pages10
ISBN (Print)0-7695-0762-X
Publication statusPublished - 2000
Event2nd NASA/DoD Workshop on Evolvable Hardware (EH-2000) - PALO ALTO, Canada
Duration: 13 Jul 200015 Jul 2000

Conference

Conference2nd NASA/DoD Workshop on Evolvable Hardware (EH-2000)
Country/TerritoryCanada
Period13/07/0015/07/00

Keywords / Materials (for Non-textual outputs)

  • EHW CHIP
  • EVOLUTION
  • HARDWARE

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