Ultra compact and low-power TDC and TAC architectures for highly-parallel implementation in time-resolved image sensors

David Stoppa; Fausto Borghetti; Justin Richardson; Richard Walker; Robert Henderson; Marek Gersbach; Edoardo Charbon

Ultra compact and low-power TDC and TAC architectures for highly-parallel implementation in time-resolved image sensors

David Stoppa, Fausto Borghetti, Justin Richardson, Richard Walker, Robert Henderson, Marek Gersbach, Edoardo Charbon

School of Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

We report on the design and characterization of three different architectures, namely two Time-to-Digital Converters (TDCs) and a Time-to-Amplitude Converter (TAC) with embedded analog-to-digital conversion, implemented in a 130-nm CMOS imaging technology. The proposed circuit solutions are conceived for implementation at pixel-level, in image sensors exploiting Single-Photon Avalanche Diodes as photodetectors. The fabricated 32x32 TDCs/TACs arrays have a pitch of 50μm in both directions while the average power consumption is between 28mW and 300mW depending on the architectural choice. The TAC achieves a time resolution of 160ps on a 20-ns time range with a differential and integral non-linearity (DNL, INL) of 0.7LSB and 1.9LSB respectively. The two TDCs have a 10-bit resolution with a minimum time resolution between 50ps and 119ps and a worst-case accuracy of ±0.5 LSB DNL and 2.4 LSB INL. An overview of the performance is given together with the analysis of the pros and cons for each architecture.

Original language	English
Title of host publication	IMEKO TC4 International Workshop on ADC Modelling, Testing and Data Converter Analysis and Design 2011, IWADC 2011 and IEEE 2011 ADC Forum
Pages	150-154
Number of pages	5
Publication status	Published - 2011

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Stoppa, D., Borghetti, F., Richardson, J., Walker, R., Henderson, R., Gersbach, M., & Charbon, E. (2011). Ultra compact and low-power TDC and TAC architectures for highly-parallel implementation in time-resolved image sensors. In IMEKO TC4 International Workshop on ADC Modelling, Testing and Data Converter Analysis and Design 2011, IWADC 2011 and IEEE 2011 ADC Forum (pp. 150-154) http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.367.7553

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title = "Ultra compact and low-power TDC and TAC architectures for highly-parallel implementation in time-resolved image sensors",

abstract = "We report on the design and characterization of three different architectures, namely two Time-to-Digital Converters (TDCs) and a Time-to-Amplitude Converter (TAC) with embedded analog-to-digital conversion, implemented in a 130-nm CMOS imaging technology. The proposed circuit solutions are conceived for implementation at pixel-level, in image sensors exploiting Single-Photon Avalanche Diodes as photodetectors. The fabricated 32x32 TDCs/TACs arrays have a pitch of 50μm in both directions while the average power consumption is between 28mW and 300mW depending on the architectural choice. The TAC achieves a time resolution of 160ps on a 20-ns time range with a differential and integral non-linearity (DNL, INL) of 0.7LSB and 1.9LSB respectively. The two TDCs have a 10-bit resolution with a minimum time resolution between 50ps and 119ps and a worst-case accuracy of ±0.5 LSB DNL and 2.4 LSB INL. An overview of the performance is given together with the analysis of the pros and cons for each architecture.",

author = "David Stoppa and Fausto Borghetti and Justin Richardson and Richard Walker and Robert Henderson and Marek Gersbach and Edoardo Charbon",

year = "2011",

language = "English",

isbn = "978-161839279-4",

pages = "150--154",

booktitle = "IMEKO TC4 International Workshop on ADC Modelling, Testing and Data Converter Analysis and Design 2011, IWADC 2011 and IEEE 2011 ADC Forum",

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Stoppa, D, Borghetti, F, Richardson, J, Walker, R, Henderson, R, Gersbach, M & Charbon, E 2011, Ultra compact and low-power TDC and TAC architectures for highly-parallel implementation in time-resolved image sensors. in IMEKO TC4 International Workshop on ADC Modelling, Testing and Data Converter Analysis and Design 2011, IWADC 2011 and IEEE 2011 ADC Forum. pp. 150-154. <http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.367.7553>

Ultra compact and low-power TDC and TAC architectures for highly-parallel implementation in time-resolved image sensors. / Stoppa, David; Borghetti, Fausto; Richardson, Justin et al.

IMEKO TC4 International Workshop on ADC Modelling, Testing and Data Converter Analysis and Design 2011, IWADC 2011 and IEEE 2011 ADC Forum. 2011. p. 150-154.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - Ultra compact and low-power TDC and TAC architectures for highly-parallel implementation in time-resolved image sensors

AU - Stoppa, David

AU - Borghetti, Fausto

AU - Richardson, Justin

AU - Walker, Richard

AU - Henderson, Robert

AU - Gersbach, Marek

AU - Charbon, Edoardo

PY - 2011

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N2 - We report on the design and characterization of three different architectures, namely two Time-to-Digital Converters (TDCs) and a Time-to-Amplitude Converter (TAC) with embedded analog-to-digital conversion, implemented in a 130-nm CMOS imaging technology. The proposed circuit solutions are conceived for implementation at pixel-level, in image sensors exploiting Single-Photon Avalanche Diodes as photodetectors. The fabricated 32x32 TDCs/TACs arrays have a pitch of 50μm in both directions while the average power consumption is between 28mW and 300mW depending on the architectural choice. The TAC achieves a time resolution of 160ps on a 20-ns time range with a differential and integral non-linearity (DNL, INL) of 0.7LSB and 1.9LSB respectively. The two TDCs have a 10-bit resolution with a minimum time resolution between 50ps and 119ps and a worst-case accuracy of ±0.5 LSB DNL and 2.4 LSB INL. An overview of the performance is given together with the analysis of the pros and cons for each architecture.

AB - We report on the design and characterization of three different architectures, namely two Time-to-Digital Converters (TDCs) and a Time-to-Amplitude Converter (TAC) with embedded analog-to-digital conversion, implemented in a 130-nm CMOS imaging technology. The proposed circuit solutions are conceived for implementation at pixel-level, in image sensors exploiting Single-Photon Avalanche Diodes as photodetectors. The fabricated 32x32 TDCs/TACs arrays have a pitch of 50μm in both directions while the average power consumption is between 28mW and 300mW depending on the architectural choice. The TAC achieves a time resolution of 160ps on a 20-ns time range with a differential and integral non-linearity (DNL, INL) of 0.7LSB and 1.9LSB respectively. The two TDCs have a 10-bit resolution with a minimum time resolution between 50ps and 119ps and a worst-case accuracy of ±0.5 LSB DNL and 2.4 LSB INL. An overview of the performance is given together with the analysis of the pros and cons for each architecture.

M3 - Conference contribution

SN - 978-161839279-4

SP - 150

EP - 154

BT - IMEKO TC4 International Workshop on ADC Modelling, Testing and Data Converter Analysis and Design 2011, IWADC 2011 and IEEE 2011 ADC Forum

ER -

Ultra compact and low-power TDC and TAC architectures for highly-parallel implementation in time-resolved image sensors

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