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Due to their streaming nature, memory bandwidth is critical for most digital signal processing applications. To accommodate these bandwidth requirements digital signal processors are typically equipped with dual memory banks that enable simultaneous access to two operands if the data is partitioned appropriately. Fully automated and compiler integrated approaches to data partitioning and memory bank assignment have, however, found little acceptance by DSP software developers. This is partly due to the inflexibility of the approach and their inability to cope with certain manual data pre-assignments, e.g. due to I/O constraints. In this paper we build upon a more flexible source-level approach where code generation targets DSP-C , using genetic programming to overcome the issues previously experienced with high-level memory bank assignment. We have evaluated our approach on an Analog Devices Tiger-SHARC DSP and achieved performance gains of up to 1.57 on 13 UTDSP benchmarks.
|Title of host publication||Proceedings of the 3rd Workshop on Statistical and Machine Learning Approaches to Architecture and Compilation|
|Number of pages||15|
|Publication status||Published - 2009|