Variation resilient subthreshold SRAM cell design technique

This article presents a circuit technique for designing a variability resilient subthreshold static random access memory (SRAM) cell. The architecture of the proposed cell is similar to the conventional 10T SRAM cell with the exception that dynamic threshold MOS is used for the read/write access FETs and cell content body bias scheme is used for bitline droppers (FETs used to drop bitlines). Moreover, the proposed bitcell utilises single differential port unlike conventional 10T bitcell which utilises dual differential ports. The proposed design offers 2.1x improvement in T-RA (read access time) and 3.2x improvement in T-WA (write access time) compared to CON10T at iso-device-area and 200 mV. It exhibits three roots in its read voltage transfer characteristic (VTC) even at 150mV showing its ability to function as a bistable circuit. The combination of write and read VTCs for write static noise margin of the proposed design also shows single root signifying its write-ability even at 150 mV. It proves its robustness against process variations by featuring narrower spread in T-RA distribution (by 1.3x) and in T-WA distribution (by 1.2x) at 200 mV.