VLSI Neural Networks

Alan Murray, Z. F. Butler, A. V. W. Smith

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract / Description of output

Strategies and design methods have been given for the construction of a hybrid analogue/digital VLSI neural network chip and a bit-serial VLSI network and board. Bit-serial and `reduced-style' arithmetic enhances the level of integration beyond more conventional digital, bit-parallel schemes. The restrictions imposed on both synaptic weight size and arithmetic precision by VLSI constraints have been examined and shown to be tolerable, using the associative memory problem as a test
Original languageUndefined/Unknown
Title of host publicationVLSI for Parallel Processing, IEE Colloquium on
Pages7/1 - 7/4
Publication statusPublished - 17 Feb 1988

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