VLSI Neural Networks

Alan Murray; Z. F. Butler; A. V. W. Smith

VLSI Neural Networks

Alan Murray, Z. F. Butler, A. V. W. Smith

School of Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

Strategies and design methods have been given for the construction of a hybrid analogue/digital VLSI neural network chip and a bit-serial VLSI network and board. Bit-serial and `reduced-style' arithmetic enhances the level of integration beyond more conventional digital, bit-parallel schemes. The restrictions imposed on both synaptic weight size and arithmetic precision by VLSI constraints have been examined and shown to be tolerable, using the associative memory problem as a test

Original language	Undefined/Unknown
Title of host publication	VLSI for Parallel Processing, IEE Colloquium on
Pages	7/1 - 7/4
Publication status	Published - 17 Feb 1988

Cite this

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title = "VLSI Neural Networks",

abstract = "Strategies and design methods have been given for the construction of a hybrid analogue/digital VLSI neural network chip and a bit-serial VLSI network and board. Bit-serial and `reduced-style' arithmetic enhances the level of integration beyond more conventional digital, bit-parallel schemes. The restrictions imposed on both synaptic weight size and arithmetic precision by VLSI constraints have been examined and shown to be tolerable, using the associative memory problem as a test",

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AB - Strategies and design methods have been given for the construction of a hybrid analogue/digital VLSI neural network chip and a bit-serial VLSI network and board. Bit-serial and `reduced-style' arithmetic enhances the level of integration beyond more conventional digital, bit-parallel schemes. The restrictions imposed on both synaptic weight size and arithmetic precision by VLSI constraints have been examined and shown to be tolerable, using the associative memory problem as a test

M3 - Conference contribution

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BT - VLSI for Parallel Processing, IEE Colloquium on

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