Weighing up the new kid on the block: Impressions of using Vitis for HPC software development

Research output: Chapter in Book/Report/Conference proceedingConference contribution


The use of reconfigurable computing, and FPGAs in particular, has strong potential in the field of High Performance Computing (HPC). However the traditionally high barrier to entry when it comes to programming this technology has, until now, precluded widespread adoption. To popularise reconfigurable computing with communities such as HPC, Xilinx have recently released the first version of Vitis, a platform aimed at making the programming of FPGAs much more a question of software development rather than hardware design. However a key question is how well this technology fulfils the aim, and whether the tooling is mature enough such that software developers using FPGAs to accelerate their codes is now a more realistic proposition, or whether it simply increases the convenience for existing experts. To examine this question we use the Himeno benchmark as a vehicle for exploring the Vitis platform for building, executing and optimising HPC codes, describing the different steps and potential pitfalls of the technology. The outcome of this exploration is a demonstration that, whilst Vitis is an excellent step forwards and significantly lowers the barrier to entry in developing codes for FPGAs, it is not a silver bullet and an underlying understanding of dataflow style algorithmic design and appreciation of the architecture is still key to obtaining good performance on reconfigurable architectures.
Original languageEnglish
Title of host publication2020 30th International Conference on Field-Programmable Logic and Applications (FPL)
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
Pages335 - 340
Number of pages6
ISBN (Electronic)978-1-7281-9902-3
ISBN (Print)978-1-7281-9903-0
Publication statusPublished - 13 Oct 2020
Event30th International Conference on Field Programmable Logic and Applications - Virtual conference, Gottenburg, Sweden
Duration: 31 Aug 20204 Sep 2020

Publication series

ISSN (Print)1946-147X
ISSN (Electronic)1946-1488


Conference30th International Conference on Field Programmable Logic and Applications
Abbreviated titleFPL 2020
Internet address


  • FPGAs
  • Reconfigurable computing
  • Vitis
  • Alveo
  • Himeno benchmark


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