Edinburgh Research Explorer

Prof Nigel Topham

Chair of Computer Systems

  1. 2019
  2. Mitigating JIT Compilation Latency in Virtual Execution Environments

    Kristien, M., Spink, T., Wagstaff, H., Franke, B., Boehm, I. & Topham, N., 14 Apr 2019, Proceedings of the 15th ACM SIGPLAN/SIGOPS International Conference on Virtual Execution Environments. Association for Computing Machinery (ACM), p. 101-107 7 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

  3. Poise: Balancing Thread-Level Parallelism and Memory System Performance in GPUs using Machine Learning

    Dublish, S., Nagarajan, V. & Topham, N., 28 Mar 2019, 2019 IEEE International Symposium on High Performance Computer Architecture (HPCA). Washington, DC, USA: Institute of Electrical and Electronics Engineers (IEEE), p. 492-505 14 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

  4. 2018
  5. High Speed Cycle-Approximate Simulation of Embedded Cache-Incoherent and Coherent Chip-Multiprocessors

    Thompson, C., Gould, M. & Topham, N., 26 Mar 2018, In : International journal of parallel programming. 46, 6, 36 p.

    Research output: Contribution to journalArticle

  6. 2017
  7. Evaluating and Mitigating Bandwidth Bottlenecks Across the Memory Hierarchy in GPUs

    Dublish, S., Nagarajan, V. & Topham, N., 13 Jul 2017, 2017 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS). Institute of Electrical and Electronics Engineers (IEEE), p. 239-248 10 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

  8. 2016
  9. Cooperative Caching for GPUs

    Dublish, S., Nagarajan, V. & Topham, N., 1 Dec 2016, In : ACM Transactions on Architecture and Code Optimization. 13, 4, p. 1-25 25 p., 39.

    Research output: Contribution to journalArticle

  10. Characterizing memory bottlenecks in GPGPU workloads

    Dublish, S., Nagarajan, V. & Topham, N., 10 Oct 2016, 2016 IEEE International Symposium on Workload Characterization (IISWC). Providence, RI, USA: Institute of Electrical and Electronics Engineers (IEEE), p. 1-2 2 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

  11. 2015
  12. Introducing SLAMBench, a performance and accuracy benchmarking methodology for SLAM

    Nardi, L., Bodin, B., Zia, M. Z., Mawer, J., Nisbet, A., Kelly, P. H. J., Davison, A. J., Luján, M., O'Boyle, M. F. P., Riley, G., Topham, N. & Furber, S., 2 Jul 2015, IEEE Intl. Conf. on Robotics and Automation (ICRA 2015). Seattle, WA, USA: Institute of Electrical and Electronics Engineers (IEEE), p. 5783-5790 8 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

  13. Efficient Dual-ISA Support in a Retargetable, Asynchronous Dynamic Binary Translator

    Spink, T., Wagstaff, H., Franke, B. & Topham, N., 2015, Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS), 2015 International Conference on. Institute of Electrical and Electronics Engineers (IEEE), p. 103 - 112 10 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

  14. 2014
  15. Efficient Code Generation in a Region-based Dynamic Binary Translator

    Spink, T., Wagstaff, H., Franke, B. & Topham, N., 2014, Proceedings of the 2014 SIGPLAN/SIGBED Conference on Languages, Compilers and Tools for Embedded Systems. New York, NY, USA: ACM, p. 3-12 10 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

  16. 2013
  17. RECAP: Region-Aware Cache Partitioning

    Sundararajan, K. T., Jones, T. M. & Topham, N. P., Oct 2013, Computer Design (ICCD), 2013 IEEE 31st International Conference on. Institute of Electrical and Electronics Engineers (IEEE), p. 294-301 8 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

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