Edinburgh Research Explorer

Nigel Topham

Chair of Computer Systems

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  1. 2020

  2. Fast and Correct Load-Link/Store-Conditional Instruction Handling in DBT Systems

    Kristien, M., Spink, T., Campbell, B., Sarkar, S., Stark, I., Franke, B., Boehm, I. & Topham, N., 1 Nov 2020, In: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 39, 11, p. 3544 - 3554 11 p.

    Research output: Contribution to journal › Article › peer-review

  3. 2019

  4. Mitigating JIT Compilation Latency in Virtual Execution Environments

    Kristien, M., Spink, T., Wagstaff, H., Franke, B., Boehm, I. & Topham, N., 14 Apr 2019, Proceedings of the 15th ACM SIGPLAN/SIGOPS International Conference on Virtual Execution Environments. Association for Computing Machinery (ACM), p. 101-107 7 p.

    Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

  5. Poise: Balancing Thread-Level Parallelism and Memory System Performance in GPUs using Machine Learning

    Dublish, S., Nagarajan, V. & Topham, N., 28 Mar 2019, 2019 IEEE International Symposium on High Performance Computer Architecture (HPCA). Washington, DC, USA: Institute of Electrical and Electronics Engineers (IEEE), p. 492-505 14 p.

    Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

  6. 2018

  7. High Speed Cycle-Approximate Simulation of Embedded Cache-Incoherent and Coherent Chip-Multiprocessors

    Thompson, C., Gould, M. & Topham, N., 1 Dec 2018, In: International journal of parallel programming. 46, 6, p. 1247–1282 36 p.

    Research output: Contribution to journal › Article › peer-review

  8. 2017

  9. Evaluating and Mitigating Bandwidth Bottlenecks Across the Memory Hierarchy in GPUs

    Dublish, S., Nagarajan, V. & Topham, N., 13 Jul 2017, 2017 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS). Institute of Electrical and Electronics Engineers (IEEE), p. 239-248 10 p.

    Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

  10. 2016

  11. Cooperative Caching for GPUs

    Dublish, S., Nagarajan, V. & Topham, N., 1 Dec 2016, In: ACM Transactions on Architecture and Code Optimization. 13, 4, p. 1-25 25 p., 39.

    Research output: Contribution to journal › Article › peer-review

  12. Characterizing memory bottlenecks in GPGPU workloads

    Dublish, S., Nagarajan, V. & Topham, N., 10 Oct 2016, 2016 IEEE International Symposium on Workload Characterization (IISWC). Providence, RI, USA: Institute of Electrical and Electronics Engineers (IEEE), p. 1-2 2 p.

    Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

  13. 2015

  14. Introducing SLAMBench, a performance and accuracy benchmarking methodology for SLAM

    Nardi, L., Bodin, B., Zia, M. Z., Mawer, J., Nisbet, A., Kelly, P. H. J., Davison, A. J., Luján, M., O'Boyle, M. F. P., Riley, G., Topham, N. & Furber, S., 2 Jul 2015, 2015 IEEE International Conference on Robotics and Automation (ICRA). Seattle, WA, USA: Institute of Electrical and Electronics Engineers (IEEE), p. 5783-5790 8 p.

    Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

  15. Efficient Dual-ISA Support in a Retargetable, Asynchronous Dynamic Binary Translator

    Spink, T., Wagstaff, H., Franke, B. & Topham, N., 2015, Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS), 2015 International Conference on. Institute of Electrical and Electronics Engineers (IEEE), p. 103 - 112 10 p.

    Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

  16. 2014

  17. Efficient Code Generation in a Region-based Dynamic Binary Translator

    Spink, T., Wagstaff, H., Franke, B. & Topham, N., 2014, Proceedings of the 2014 SIGPLAN/SIGBED Conference on Languages, Compilers and Tools for Embedded Systems. New York, NY, USA: ACM, p. 3-12 10 p.

    Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

  18. 2013

  19. RECAP: Region-Aware Cache Partitioning

    Sundararajan, K. T., Jones, T. M. & Topham, N. P., Oct 2013, Computer Design (ICCD), 2013 IEEE 31st International Conference on. Institute of Electrical and Electronics Engineers (IEEE), p. 294-301 8 p.

    Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

  20. High speed cycle approximate simulation for cache-incoherent MPSoCs

    Gould, M., Thompson, C. & Topham, N., Jul 2013, Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XIII), 2013 International Conference on. Institute of Electrical and Electronics Engineers (IEEE), p. 88 - 95

    Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

  21. A Parallel Dynamic Binary Translator for Efficient Multi-Core Simulation

    Almer, O., Boehm, I., von Koch, T. E., Franke, B., Kyle, S., Seeker, V., Thompson, C. & Topham, N., Apr 2013, In: International journal of parallel programming. 41, 2, p. 212-235 24 p.

    Research output: Contribution to journal › Article › peer-review

  22. The Smart Cache: An Energy-Efficient Cache Architecture Through Dynamic Adaptation

    Sundararajan, K. T., Jones, T. M. & Topham, N. P., Apr 2013, In: International journal of parallel programming. 41, 2, p. 305-330 26 p.

    Research output: Contribution to journal › Article › peer-review

  23. Early partial evaluation in a JIT-compiled, retargetable instruction set simulator generated from a high-level architecture description

    Gould, M., Wagstaff, H., Franke, B. & Topham, N., 2013, Publishing Proceedings of the 50th Annual Design Automation Conference - DAC 2013. ACM, 21

    Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

  24. 2012

  25. Cooperative partitioning: Energy-efficient cache partitioning for high-performance CMPs

    Sundararajan, K. T., Porpodas, V., Jones, T. M., Topham, N. P. & Franke, B., 1 Feb 2012, High Performance Computer Architecture (HPCA), 2012 IEEE 18th International Symposium on. Institute of Electrical and Electronics Engineers (IEEE), p. 1-12 12 p.

    Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

  26. Design Space Exploration of Hybrid Ultra Low Power Branch Predictors

    Bielby, M., Gould, M. & Topham, N., 2012, Architecture of Computing Systems – ARCS 2012: 25th International Conference, Munich, Germany, February 28 - March 2, 2012. Proceedings. SpringerLink, Vol. 7179. p. 184-199 (Lecture Notes in Computer Science; vol. 7179).

    Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

  27. Efficiently Parallelizing Instruction Set Simulation of Embedded Multi-core Processors Using Region-based Just-in-time Dynamic Binary Translation

    Kyle, S., Böhm, I., Franke, B., Leather, H. & Topham, N., 2012, Proceedings of the 13th ACM SIGPLAN/SIGBED International Conference on Languages, Compilers, Tools and Theory for Embedded Systems. New York, NY, USA: ACM, p. 21-30 10 p. (LCTES '12).

    Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

  28. Energy-efficient Cache Partitioning for Future CMPs

    Sundararajan, K. T., Jones, T. M. & Topham, N. P., 2012, Proceedings of the 21st International Conference on Parallel Architectures and Compilation Techniques. New York, NY, USA: ACM, p. 465-466 2 p. (PACT '12).

    Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

  29. Predicting best design trade-offs: a case study in processor customization

    Zuluaga, M., Bonilla, E. & Topham, N., 2012, Proceedings of the Conference on Design, Automation and Test in Europe. San Jose, CA, USA: EDA Consortium, p. 1030-1035 6 p.

    Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

  30. 2011

  31. Scalable multi-core simulation using parallel dynamic binary translation

    Almer, O., Böhm, I., Von Koch, T. E., Franke, B., Kyle, S., Seeker, V., Thompson, C. & Topham, N., 7 Nov 2011, Proceedings - 2011 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation, IC-SAMOS 2011. p. 190-199 10 p. 6045461

    Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

  32. Smart Cache: A Self Adaptive Cache Architecture for Energy Efficiency

    Sundararajan, K. T., Jones, T. M. & Topham, N., 1 Jul 2011, Proceedings of the International Symposium on Systems, Architectures, Modeling, and Simulation (SAMOS'11). p. 41-50 10 p.

    Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

  33. Virtual Manycore platforms: Moving towards 100 #x002B; processor cores

    Leupers, R., Eeckhout, L., Martin, G., Schirrmeister, F., Topham, N. & Chen, X., 1 Mar 2011, Design, Automation Test in Europe Conference Exhibition (DATE), 2011. Institute of Electrical and Electronics Engineers (IEEE), p. 1-6 6 p.

    Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

  34. A Learning-Based Approach to the Automated Design of MPSoC Networks

    Almer, O., Topham, N. & Franke, B., 2011, Architecture of Computing Systems - ARCS 2011: 24th International Conference, Como, Italy, February 24-25, 2011. Proceedings. Berekovic, M., Fornaciari, W., Brinkschulte, U. & Silvano, C. (eds.). Springer-Verlag Berlin Heidelberg, p. 243-258 16 p. (Lecture Notes in Computer Science; vol. 6566).

    Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

  35. A Reconfigurable Cache Architecture for Energy Efficiency

    Sundararajan, K. T., Jones, T. M. & Topham, N., 2011, Proceedings of the 8th ACM International Conference on Computing Frontiers. New York, NY, USA: ACM, p. 9:1-9:2 2 p. (CF '11).

    Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

  36. Cycle-Accurate Performance Modelling in an Ultra-Fast Just-In-Time Dynamic Binary Translation Instruction Set Simulator

    Bohm, I., Franke, B. & Topham, N., 2011, In: Transactions on High Performance and Embedded Architecture and Compilation. 5, 4, 20 p.

    Research output: Contribution to journal › Article › peer-review

  37. Generalized just-in-time trace compilation using a parallel task farm in a dynamic binary translator

    Bohm, I., Edler von Koch, T. J. K., Kyle, S. C., Franke, B. & Topham, N., 2011, Proceedings of the 32nd ACM SIGPLAN conference on Programming Language Design and Implementation (PLDI '11). New York, NY, USA: ACM, p. 74-85 12 p.

    Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

  38. Selecting the optimal system: automated design of application-specific systems-on-chip

    Almer, O., Gould, M., Topham, N. & Franke, B., 2011, Proceedings of the 4th International Workshop on Network on Chip Architectures - NoCArc 2011. ACM, p. 43-50

    Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

  39. The EnCore Microprocessor

    Topham, N., 2011

    Research output: Non-textual form › Artefact

  40. 2010

  41. Cycle-accurate performance modelling in an ultra-fast just-in-time dynamic binary translation instruction set simulator

    Bohm, I., Franke, B. & Topham, N., 1 Jul 2010, International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS 2010). p. 1-10 10 p.

    Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

  42. Exploring the unified design-space of custom-instruction selection and resource sharing

    Zuluaga, M. & Topham, N., 1 Jul 2010, Embedded Computer Systems (SAMOS), 2010 International Conference on. p. 282-291 10 p.

    Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

  43. Adaptive High-Speed Processor Simulation

    Topham, N., Franke, B., Jones, D. & Powell, D., 2010, Processor and System-on-Chip Simulation. Leupers, R. & Temam, O. (eds.). Springer US, p. 145-159 15 p.

    Research output: Chapter in Book/Report/Conference proceeding › Chapter (peer-reviewed) › peer-review

  44. 2009

  45. Design-Space Exploration of Resource-Sharing Solutions for Custom Instruction Set Extensions

    Zuluaga, M. & Topham, N., 1 Dec 2009, In: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 28, 12, p. 1788-1801 14 p.

    Research output: Contribution to journal › Article › peer-review

  46. Code transformation and instruction set extension

    Murray, A. C., Bennett, R. V., Franke, B. & Topham, N., 1 Jul 2009, In: ACM Transactions on Embedded Computing Systems. 8, 4, 31 p., 26.

    Research output: Contribution to journal › Article › peer-review

  47. On the scalability of storage sub-system back-end networks

    Li, Y., Courtney, T., Ibbett, R. N. & Topham, N., 2 Feb 2009, 2008 International Symposium on Performance Evaluation of Computer and Telecommunication Systems. Institute of Electrical and Electronics Engineers (IEEE), p. 464-471 8 p.

    Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

  48. An End-to-End Design Flow for Automated Instruction Set Extension and Complex Instruction Selection Based on GCC

    Almer, O., Bennett, R., Böhm, I., Murray, A., Qu, X., Zuluaga, M., Franke, B. & Topham, N. P., 2009, GROW'09: Proceedings of the 1st International Workshop on GCC Research Opportunities. p. 1-12 12 p.

    Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

  49. High Speed CPU Simulation using LTU Dynamic Binary Translation

    Jones, D. & Topham, N. P., 2009, 4th International Conference on High Performance Embedded Architectures and Compilers (HiPEAC). Springer Berlin Heidelberg, p. 50-64 15 p. (Lecture Notes in Computer Science).

    Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

  50. Introducing Control-Flow Inclusion to Support Pipelining in Custom Instruction Set Extensions

    Zuluaga, M., Kluter, T., Brisk, P., Topham, N. P. & Ienne, P., 2009, SASP'09: Proceedings of the 7th IEEE Symposium on Application Specific Processors. p. 114-121 8 p.

    Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

  51. 2008

  52. Resource Sharing in Custom Instruction Set Extensions

    Zuluaga, M. & Topham, N., 1 Jun 2008, Application Specific Processors, 2008. SASP 2008. Symposium on. Institute of Electrical and Electronics Engineers (IEEE), p. 7-13 7 p.

    Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

  53. Translating a simulation-target memory access to a simulation-host memory access

    Topham, N. P., 1 May 2008, Patent No. WO 2008053160 A1

    Research output: Patent

  54. On The Scalability of Storage Sub-system Back-end Network

    Li, Y., Courtney, T., Topham, N. P. & Ibbett, R. N., 2008, SPECTS 2008.

    Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

  55. 2007

  56. Combining Source-to-source Transformations and Processor Instruction Set Extensions for the Automated Design-space Exploration of Embedded Systems

    Bennett, R. V., Murray, A. C., Franke, B. & Topham, N., 1 Jun 2007, LCTES '07 Proceedings of the 2007 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems. ACM, p. 83-92 10 p.

    Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

  57. Synthetic Trace-Driven Simulation of Cache Memory

    Hassan, R., Harris, A., Topham, N. & Efthymiou, A., 1 May 2007, Advanced Information Networking and Applications Workshops, 2007, AINAW '07. 21st International Conference on. Vol. 1. p. 764-771 8 p.

    Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

  58. Systolic-array based systems and methods for performing block matching in motion compensation

    Topham, N., 1 Mar 2007, Patent No. US 20070071101 A1

    Research output: Patent

  59. A Hybrid Markov Model for Accurate Memory Reference Generation

    Hassan, R., Harris, A., Topham, N. P. & Efthymiou, A., 2007, Proceedings of the International MultiConference of Engineers and Computer Scientists 2007, IMECS 2007, March 21-23, 2007, Hong Kong, China. p. 550-555 6 p.

    Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

  60. Architecture for microprocessor-based systems including simd processing unit and associated systems and methods

    Wong, K-L., Graham, C., Topham, N., Jones, S., Aristodemou, A., Nemouchi, Y. & Lim, S. C., 2007, IPC No. WO 2007049150, Priority date 28 Sep 2005

    Research output: Patent

  61. Parameterizable clip instruction and method of performing a clip operation using the same

    Topham, N., Nemouchi, Y., Jones, S., Graham, C., Wong, K-L. & Aristodemou, A., 2007, Patent No. 20070074007, Priority date 28 Sep 2005

    Research output: Patent

  62. Work in Progress: On the Scalability of Storage Sub-system Back-end Network

    Li, Y., Courtney, T., Ibbett, R. N. & Topham, N., 2007, Proceedings of the 5th USENIX Conference on File and Storage Technologies. Berkeley, CA, USA: USENIX Association, p. 7-7 1 p. (FAST '07).

    Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

  63. Work in Progress: Performance Evaluation of RAID6 Systems

    Li, Y., Courtney, T., Ibbett, R. N. & Topham, N. P., 2007, WiP of FAST. 1 p.

    Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

  64. 2006

  65. Challenges to Automatic Customization

    Topham, N. P., 2006, Customizable Embedded Processors: Design Technologies and Applications. Lenne, P. & Leupers, R. (eds.). Morgan Kaufman, p. 185-208 24 p.

    Research output: Chapter in Book/Report/Conference proceeding › Chapter

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