Edinburgh Research Explorer

Cycle-accurate performance modelling in an ultra-fast just-in-time dynamic binary translation instruction set simulator

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Original languageEnglish
Title of host publicationInternational Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS 2010)
Number of pages10
ISBN (Electronic)978-1-4244-7938-2
Publication statusPublished - 1 Jul 2010


Instruction set simulators (ISS) are vital tools for compiler and processor architecture design space exploration and verification. State-of-the-art simulators using just-in-time (JIT) dynamic binary translation (DBT) techniques are able to simulate complex embedded processors at speeds above 500 MIPS. However, these functional ISS do not provide microarchitectural observability. In contrast, low-level cycle-accurate ISS are too slow to simulate full-scale applications, forcing developers to revert to FPGA-based simulations. In this paper we demonstrate that it is possible to run ultra-high speed cycle-accurate instruction set simulations surpassing FPGA-based simulation speeds. We extend the JIT DBT engine of our ISS and augment JIT generated code with a verified cycle-accurate processor model. Our approach can model any microarchitectural configuration, does not rely on prior profiling, instrumentation, or compilation, and works for all binaries targeting a state-of-the-art embedded processor implementing the ARCompact #x2122; instruction set architecture (ISA). We achieve simulation speeds up to 63 MIPS on a standard #x00D7;86 desktop computer, whilst the average cycle-count deviation is less than 1.5% for the industry standard EEMBC and COREMARK benchmark suites.

    Research areas

  • FPGA-based simulations, compiler architecture design space exploration, cycle-accurate performance modelling, design space verification, embedded processor, industry standard CoreMark benchmark suites, industry standard EEMBC benchmark suites, instruction set architecture, microarchitectural observability, processor architecture design space exploration, ultra-fast just-in-time dynamic binary translation instruction set simulator, instruction sets

Download statistics

No data available

ID: 701574