Edinburgh Research Explorer

Early partial evaluation in a JIT-compiled, retargetable instruction set simulator generated from a high-level architecture description

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Original languageEnglish
Title of host publicationPublishing Proceedings of the 50th Annual Design Automation Conference - DAC 2013
PublisherACM
ISBN (Print)978-1-4503-2071-9
DOIs
StatePublished - 2013

Abstract

Modern processor design tools integrate in their workflows generators for instruction set simulators (Iss) from architecture descriptions. Whilst these generated simulators are useful for design evaluation and software development, they suffer from poor performance. We present an ultra-fast Jit-compiled Iss generated from an ArchC description. We also introduce a novel partial evaluation optimisation, which further improves Jit compilation time and code quality. This results in a simulation rate of 510Mips for an Arm target across 45 Eembc and Spec benchmarks. On average, our Iss is 1.7 times faster than Simit-Arm, one of the fastest Iss generated from an architecture description.

ID: 14612505