Edinburgh Research Explorer

Evaluating and Mitigating Bandwidth Bottlenecks Across the Memory Hierarchy in GPUs

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Standard

Evaluating and Mitigating Bandwidth Bottlenecks Across the Memory Hierarchy in GPUs. / Dublish, Saumay; Nagarajan, Vijay; Topham, Nigel.

2017 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS). Institute of Electrical and Electronics Engineers (IEEE), 2017. p. 239-248.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Harvard

Dublish, S, Nagarajan, V & Topham, N 2017, Evaluating and Mitigating Bandwidth Bottlenecks Across the Memory Hierarchy in GPUs. in 2017 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS). Institute of Electrical and Electronics Engineers (IEEE), pp. 239-248, 2017 IEEE International Symposium on Performance Analysis of Systems and Software, Santa Rosa, United States, 24/04/17. https://doi.org/10.1109/ISPASS.2017.7975295

APA

Dublish, S., Nagarajan, V., & Topham, N. (2017). Evaluating and Mitigating Bandwidth Bottlenecks Across the Memory Hierarchy in GPUs. In 2017 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS) (pp. 239-248). Institute of Electrical and Electronics Engineers (IEEE). https://doi.org/10.1109/ISPASS.2017.7975295

Vancouver

Dublish S, Nagarajan V, Topham N. Evaluating and Mitigating Bandwidth Bottlenecks Across the Memory Hierarchy in GPUs. In 2017 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS). Institute of Electrical and Electronics Engineers (IEEE). 2017. p. 239-248 https://doi.org/10.1109/ISPASS.2017.7975295

Author

Dublish, Saumay ; Nagarajan, Vijay ; Topham, Nigel. / Evaluating and Mitigating Bandwidth Bottlenecks Across the Memory Hierarchy in GPUs. 2017 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS). Institute of Electrical and Electronics Engineers (IEEE), 2017. pp. 239-248