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High level programming abstractions for leveraging hierarchical memories with micro-core architectures

Research output: Contribution to journalArticlepeer-review

Standard

High level programming abstractions for leveraging hierarchical memories with micro-core architectures. / Jamieson, Maurice; Brown, Nicholas.

In: Journal of Parallel and Distributed Computing, Vol. 138, 30.04.2020, p. 128-138.

Research output: Contribution to journalArticlepeer-review

Harvard

Jamieson, M & Brown, N 2020, 'High level programming abstractions for leveraging hierarchical memories with micro-core architectures', Journal of Parallel and Distributed Computing, vol. 138, pp. 128-138. https://doi.org/10.1016/j.jpdc.2019.11.011

APA

Jamieson, M., & Brown, N. (2020). High level programming abstractions for leveraging hierarchical memories with micro-core architectures. Journal of Parallel and Distributed Computing, 138, 128-138. https://doi.org/10.1016/j.jpdc.2019.11.011

Vancouver

Jamieson M, Brown N. High level programming abstractions for leveraging hierarchical memories with micro-core architectures. Journal of Parallel and Distributed Computing. 2020 Apr 30;138:128-138. https://doi.org/10.1016/j.jpdc.2019.11.011

Author

Jamieson, Maurice ; Brown, Nicholas. / High level programming abstractions for leveraging hierarchical memories with micro-core architectures. In: Journal of Parallel and Distributed Computing. 2020 ; Vol. 138. pp. 128-138.