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High speed cycle approximate simulation for cache-incoherent MPSoCs

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Original languageEnglish
Title of host publicationEmbedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XIII), 2013 International Conference on
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
Pages88 - 95
ISBN (Print)978-1-4799-0103-6
DOIs
Publication statusPublished - Jul 2013
Event2013 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XIII) - Samos Island, Greece, United Kingdom
Duration: 15 Jul 201318 Jul 2013

Conference

Conference2013 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XIII)
CountryUnited Kingdom
Period15/07/1318/07/13

Abstract

We present a new high speed cycle-approximate simulator, addressing an important, neglected category of multi-core systems: deeply-embedded cache-incoherent MPSoCs. We take advantage of the unique properties of these systems to increase the parallelism of the simulation. In doing so we achieve performance not possible using previous simulation techniques, without compromising the accuracy of the results. We present quantitative performance results across a large range of simulated NoC designs, comprising 1 to 64 cores. On average we simulate at 5.9 MIPS, with simulation speeds reaching 373 MIPS in the best case. Comparing against FPGA implementations we demonstrate that the simulator manages this with an average timing error of only 2.1%.

ID: 25291051