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Integrating Algorithmic Parameters into Benchmarking and Design Space Exploration in 3D Scene Understanding

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Original languageEnglish
Title of host publicationParallel Architecture and Compilation Techniques (PACT), 2016 International Conference on
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
Number of pages13
ISBN (Electronic)978-1-4503-4121-9
ISBN (Print)978-1-5090-5308-7
StatePublished - 1 Dec 2016
Event25th International Conference on Parallel Architectures and Compilation Techniques - Haifa, Israel
Duration: 11 Sep 201615 Sep 2016


Conference25th International Conference on Parallel Architectures and Compilation Techniques
Abbreviated titlePACT 2016
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System designers typically use well-studied benchmarks to evaluate and improve new architectures and compilers. We design tomorrow’s systems based on yesterday’s applications. In this paper we investigate an emerging application, 3D scene understanding, likely to be significant in the mobile space in the near future. Until now, this application could only run in real-time on desktop GPUs. In this work, we examine how it can be mapped to power constrained embedded systems. Key to our approach is the idea of incremental co-design exploration, where optimization choices that concern the domain layer are incrementally explored together with low-level compiler and architecture choices. The goal of this exploration is to reduce execution time while minimizing power and meeting our quality of result objective. As the design space is too large to exhaustively evaluate, we use active learning based on a random forest predictor to find good designs. We show that our approach can, for the first time, achieve dense 3D mapping and tracking in the real-time range within a 1W power budget on a popular embedded device. This is a 4.8x execution time improvement and a 2.8x power reduction compared to the state-of-the-art.


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