Edinburgh Research Explorer

Poise: Balancing Thread-Level Parallelism and Memory System Performance in GPUs using Machine Learning

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Standard

Poise: Balancing Thread-Level Parallelism and Memory System Performance in GPUs using Machine Learning. / Dublish, Saumay; Nagarajan, Vijayanand; Topham, Nigel.

2019 IEEE International Symposium on High Performance Computer Architecture (HPCA). Washington, DC, USA : Institute of Electrical and Electronics Engineers (IEEE), 2019. p. 492-505.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Harvard

Dublish, S, Nagarajan, V & Topham, N 2019, Poise: Balancing Thread-Level Parallelism and Memory System Performance in GPUs using Machine Learning. in 2019 IEEE International Symposium on High Performance Computer Architecture (HPCA). Institute of Electrical and Electronics Engineers (IEEE), Washington, DC, USA, pp. 492-505, 25th IEEE International Symposium on High-Performance Computer Architecture, Washington D.C., United States, 16/02/19. https://doi.org/10.1109/HPCA.2019.00061

APA

Dublish, S., Nagarajan, V., & Topham, N. (2019). Poise: Balancing Thread-Level Parallelism and Memory System Performance in GPUs using Machine Learning. In 2019 IEEE International Symposium on High Performance Computer Architecture (HPCA) (pp. 492-505). Institute of Electrical and Electronics Engineers (IEEE). https://doi.org/10.1109/HPCA.2019.00061

Vancouver

Dublish S, Nagarajan V, Topham N. Poise: Balancing Thread-Level Parallelism and Memory System Performance in GPUs using Machine Learning. In 2019 IEEE International Symposium on High Performance Computer Architecture (HPCA). Washington, DC, USA: Institute of Electrical and Electronics Engineers (IEEE). 2019. p. 492-505 https://doi.org/10.1109/HPCA.2019.00061

Author

Dublish, Saumay ; Nagarajan, Vijayanand ; Topham, Nigel. / Poise: Balancing Thread-Level Parallelism and Memory System Performance in GPUs using Machine Learning. 2019 IEEE International Symposium on High Performance Computer Architecture (HPCA). Washington, DC, USA : Institute of Electrical and Electronics Engineers (IEEE), 2019. pp. 492-505