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Rigorous engineering for hardware security: Formal modelling and proof in the CHERI design and implementation process

Research output: Chapter in Book/Report/Conference proceedingConference contribution

  • Kyndylan Nienhuis
  • Alexandre Joannou
  • Thomas Bauereiss
  • Anthony Fox
  • Michael Roe
  • Brian Campbell
  • Matthew Naylor
  • Robert M. Norton
  • Simon W. Moore
  • Peter G. Neumann
  • Ian Stark
  • Robert N. M. Watson
  • Peter Sewell

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Documents

https://ieeexplore.ieee.org/document/9152777
Original languageEnglish
Title of host publication2020 IEEE Symposium on Security and Privacy (SP)
Place of PublicationSan Francisco, CA, USA
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
Pages1003-1020
Number of pages18
ISBN (Electronic)978-1-7281-3497-0
ISBN (Print)978-1-7281-3498-7
DOIs
Publication statusPublished - 30 Jul 2020
Event41st IEEE Symposium on Security and Privacy - The Hyatt Regency, San Francisco, United States
Duration: 18 May 202020 May 2020
Conference number: 41
http://www.ieee-security.org/TC/SP2020/

Publication series

Name
PublisherIEEE
ISSN (Print)1081-6011
ISSN (Electronic)2375-1207

Conference

Conference41st IEEE Symposium on Security and Privacy
Abbreviated titleSP 2020
CountryUnited States
CitySan Francisco
Period18/05/2020/05/20
Internet address

Abstract

The root causes of many security vulnerabilities include a pernicious combination of two problems, often regarded as inescapable aspects of computing. First, the protection mechanisms provided by the mainstream processor architecture and C/C++ language abstractions, dating back to the 1970s and before, provide only coarse-grain virtual-memory-based protection. Second, mainstream system engineering relies almost exclusively on test-and-debug methods, with (at best) prose specifications.These methods have historically sufficed commercially for much of the computer industry, but they fail to prevent large numbers of exploitable bugs, and the security problems that this causes are becoming ever more acute.

In this paper we show how more rigorous engineering methods can be applied to the development of a new security-enhanced processor architecture, with its accompanying hardware implementation and software stack. We use formal models of the complete instruction-set architecture (ISA) at the heart of the design and engineering process, both in lightweight ways that support and improve normal engineering practice – as documentation, in emulators used as a test oracle for hardware and for running software, and for test generation – and for formal verification. We formalise key intended security properties of the design, and establish that these hold with mechanised proof. This is for the same complete ISA models (complete enough to boot operating systems), without idealisation.

We do this for CHERI, an architecture with hardware capabilities that supports fine-grained memory protection and scalable secure compartmentalisation, while offering a smooth adoption path for existing software. CHERI is a maturing research architecture, developed since 2010, with work now underway on an Arm industrial prototype to explore its possible adoption in mass-market commercial processors. The rigorous engineering work described here has been an integral part of its development to date, enabling more rapid and confident experimentation, and boosting confidence in the design.

Event

41st IEEE Symposium on Security and Privacy

18/05/2020/05/20

San Francisco, United States

Event: Conference

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